In many digital systems, it is sometimes necessary to move signals and signals containing data between different clock domains. These different clock domains may be at completely independent frequencies and phases, different only in frequency, different only in phase, or one clock domain may be derivative of the other clock domain. Problems can occur when moving signals between clock domains. If a flip-flop is clocking in a signal that originated in another clock domain, there may be no way to guarantee the necessary set-up and hold time for the flip-flop. As a result, it may not be possible to determine on which clock edge the flip-flop will detect a transition on the data input. Or, even worse, the flip-flop may become unstable and begin oscillating if the data input is transitioning at the same time as the active clock edge.
Meta-stable flip-flops (also referred to herein as meta-flops) have been proposed for dealing with these issues of meta-stability with some success. However, when applied to a data bus with many signals, using a meta-flop for each signal of the data bus can consume valuable real estate on semiconductor devices. In addition, if the various data signals on the data bus arrive at slightly different times, it may be impossible to guarantee that all the meta-flops on the data bus are clocking consistent data.
As another means of passing data between clock domains when going from a high-speed clock domain to a lower-speed clock domain a First-In-First-Out (FIFO) buffer may be used to buffer the data. However, a FIFO may only be practical when the data in the high-speed domain are bursty in nature, such that the average bandwidth in the high-speed domain does not exceed the maximum bandwidth in the low-speed domain. In addition, if the clocks are completely unrelated, a FIFO design may still require meta-flops on the inputs and include all the problems that meta-flops on busses may have. Moreover, FIFOs also consume large areas of a semiconductor die.
There is a need for improved apparatuses and methods for transferring information on data busses from one clock domain to another clock domain. Furthermore, there is a need for apparatuses and methods that can perform this clock domain crossing while preserving temporal characteristics of the information that may be important to some systems.